Maeesha Binte Hashem

PhD Student @ University of Minnesota

I am a first-year Ph.D. student in Electrical and Computer Engineering at University of Minnesota Twin Cities. I completed my Master’s in Electrical and Computer Engineering at University of Illinois Chicago, and my Bachelor’s in Electrical and Electronic Engineering at Bangladesh University of Engineering and Technology (BUET).

During my Master’s, I had the opportunity to complete a co-op internship at Intel in Fall 2024. Prior to that, I worked as a Physical Design Engineer at Neural Semiconductor in Dhaka, Bangladesh after completing my undergraduate studies.

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Minneapolis, MN, USA

Research

My research focuses on evaluating and optimizing computer architectures for emerging workloads. I am broadly interested in Machine Learning, Compilers, and VLSI Design.

TimeFloats: Train-in-Memory with Time-Domain

In this work, we propose “TimeFloats,” an efficient train-in-memory architecture that performs 8-bit floating-point scalar product operations in the time domain. While building on the compute-in-memory paradigm’s integrated storage and inferential computations, TimeFloats additionally enables floating-point computations, thus facilitating DNN training within the same memory structures. Traditional compute-in-memory approaches face challenges such as higher power consumption and increased design complexity; in contrast, TimeFloats leverages time-domain signal processing to avoid conventional domain converters, reducing power consumption and noise sensitivity while enabling high-resolution computations.

Towards Model-Size Agnostic, Compute-Free, Memorization-based Inference of Deep Learning

This paper proposes a novel memorization-based inference (MBI) that is compute-free and only requires lookups. Specifically, our work capitalizes on the inference mechanism of the recurrent attention model (RAM), where only a small window of input domain (glimpse) is processed in a one-time step, and the outputs from multiple glimpses are combined through a hidden vector to determine the overall classification output of the problem. By leveraging the low-dimensionality of glimpse, our inference procedure stores key-value pairs comprising of glimpse location, patch vector, etc. in a table. The computations are obviated during inference by utilizing the table to read out key-value pairs and performing compute-free inference by memorization.

Experience

My professional journey.

System Architect and Design Engineer Intern

Intel Corporation

Jan 2024 — Dec 2025

Designed a hardware cost model framework to evaluate and explore design space for fully digital compute-in-memory macros.

Graduate Teaching Assistant

University of Illinois Chicago

Jan 2021 — Dec 2025

Conducted lab sessions, graded exams and projects, proctored exams, and held regular office hours to support undergraduate instruction in core ECE courses.
Assisted in delivering course content and supporting student understanding in both theoretical and hands-on lab environments.

Courses Supported: ECE 467 – Introduction to VLSI Design, ECE 266 – Introduction to Embedded Systems, ECE 317 – Digital Signal Processing, ECE 366 – Computer Organization, and ECE 265 – Introduction to Logic Design.

Physical Design Engineer

Neural Semiconductor Limited

Jan 2020 — Dec 2021

Led full-chip physical design (netlist to GDSII) for a 40nm AI chip with over 500,000 instances, executing key implementation stages including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off (DRC, LVS, LEC, ERC).
Performed RTL-to-GDSII physical implementation on multiple 45nm in-house blocks, focusing on timing closure and power optimization.
Developed automation scripts using TCL, Bash, and Python for IP block and pin placement, LEF/DEF/Lib file generation, and tool output parsing and flow integration.
Customized and extended YAML-based design automation flows for reusable IP integration.
Completed Cadence-certified training on Genus Synthesis Solution and Innovus Implementation System.
Participated in fabless semiconductor manufacturing training, gaining cross-functional flow awareness.

Education

My academic background.

PhD in Electrical and Computer Engineering

University of Minnesota Twin Cities

Jan 2025 — Present

GPA: 3.83/4.00

Core Coursework: EE 8310: Advanced Topics in VLSI, EE 5340: Introduction to Quantum Computing and Physical Basics of Computing, CSCI 5523: Introduction to Data Mining, EE 5324: VLSI Design II, and EE 5393: Circuits, Computation, and Biology.

MSc in Electrical and Computer Engineering

University of Illinois Chicago

Aug 2021 — May 2025

GPA: 3.59/4.0

Core Coursework: CS 401 (Computer Algorithms I), ECE 407 (Pattern Recognition I), ECE 465 (Digital Systems Design), ECE 466 (Advanced Computer Architecture), ECE 467 (Introduction to VLSI Design), ECE 491 (Introduction to Neural Networks), ECE 540 (Physics of Semiconductor Devices), ECE 559 (Neural Networks), ECE 566 (Parallel Processing), ECE 567 (Advanced VLSI Design), ECE 568 (Advanced Micro Architecture), and ECE 569 (High-Performance Process & Systems).

MSc Thesis: Exploring Time-Domain Floating-Point Computation for Neural Network Training in Compute-in-Memory Systems

[Read Thesis]

B.Sc in Electrical and Electronic Engineering

Bangladesh University of Engineering and Technology

Jan 2015 — Dec 2019

Major: Electronics | Minor: Power

GPA: 3.48/4.00

Core Coursework: Electrical Circuits, Electronic Circuit Simulation, Electronics, Electromagnetics, Numerical Technique, Continuous Signals and Linear Systems, Digital Logic Design, Energy Conversion, Power System, Power Electronics, Electrical Properties of Materials, Electrical Services Design, Microprocessor and Interfacing, Analog Integrated Circuit, Control System, Solid State Device, Compound Semiconductor and Hetero Junction Devices, VLSI, Optoelectronics, and Semiconductor Device Theory.

B.Sc. Thesis: Robust Spin Electron Transport in the Presence of Magnetic Field in Square Lattice: Explored spin-resolved electron transport properties in two-dimensional square lattice systems under external magnetic fields. Analyzed robustness and interference effects using quantum transport theory and simulation tools.